Computer Architecture

Start Date
30/07/2017

End Date
06/10/2017

Enrollment End Date
06/10/2017

No. of
Enrollments
1451 students

No course
syllabus uploaded

Created by

Madhu Mutyam
IIT Madras
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Course Language
English
Course Type
Scheduled
Video transcripts
Course Category
Engineering
Learning Path
Undergraduate
Course Length
0 Hours
Weekly time commitments
0 Hours
Course Completion
Exam Date
To be announced
Credits
0

32

Tutorials

8

Tests

0

Assignment

0

Article

0

Weekly Reading list

Overview

Computer architecture course deals with instruction set architecture, microarchitecture and efficient implementation of microarchitecture. Understanding the computer architecture concepts is essential for students interested in hardware, processor design, compilers, and operating systems. 

In the last four decades, the number of transistors in a chip has increased from few thousands to few billions. In order to utilize the available transistors in a chip to improve computational power, various micro-architectural techniques have been proposed, which lead to the design of variety of processors, from simple in-order pipeline processors to recent multi-core processors. The course provides a detailed understanding of various processor microarchitectural designs, which include in-order scalar pipeline design, out-of-order superscalar processor design, and multicore processor design.

Pre-requisites:
Digital Logic Design or Digital Circuits and Systems, Computer Organization

COURSE SYLLABUS
In the last four decades, the number of transistors in a chip has increased from few thousands to few billions. In order to utilize the available transistors in a chip to improve computational power, various micro-architectural techniques have been proposed, which lead to the design of variety of processors, from simple in-order pipeline processors to recent multi-core processors. The course provides a detailed understanding of the fundamentals of computer architecture, such as instruction-set principles, micro-architectural techniques, and memory hierarchy design.  

SYLLABUS OUTLINE

 Week 1:  Introduction, Instruction Set Principles
Week 2:  Memory Hierarchy Design – Cache Memory Hierarchy
Week 3:  Memory Hierarchy Design – Main Memory Design
Week 4:  Fundamentals of Pipelining
Week 5:  Instruction Level Parallelism
Week 6:  Out-of-Order Execution 
Week 7:  Thread-Level Parallelism – Multi-core Processors
Week 8:  Thread-Level Parallelism – Cache Coherency Problem, Synchronization, and Memory Consistency

To access the content, please enroll in the course.

Faculty

Madhu Mutyam


Dr. Madhu Mutyam is an Associate Professor in the Department of Computer Science and Engineering, IIT Madras. His research interests include multi-core architectures, specifically, issues related to memory system design and network-on-chip.

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