Digital Circuits and Systems

Start Date
01/07/2018

End Date
07/09/2018

No. of
Enrollments
1414 students

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syllabus uploaded

Created by

Shankar Balachandran
IIT Madras
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Course Language
English
Course Type
Scheduled
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Course Category
Engineering
Learning Path
Undergraduate
Course Length
0 Hours
Weekly time commitments
0 Hours
Course Completion
Exam Date
To be announced
Credits
0

96

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Weekly Reading list

Overview

Digital circuits are the basic blocks of modern electronic devices like mobile phones, digital cameras, microprocessors and several other devices. In this course, we will learn the fundamentals of digital circuits and how to engineer the building blocks that go into digital subsystems. We will first learn the basics of Boolean algebra and combinational logic. We will then have a thorough treatment of sequential circuits and state machines. Finally, we will learn how to analyze the performance of digital circuits and how to design high performance circuits. The course will emphasize both on the design philosophy and good design practices. Students will also get an exposure to Verilog, a popular hardware modeling language.

COURSE OUTLINE:

Week 1:
Introduction to Digital Circuits, Digital Hardware Design Process, Boolean Logic, Truth Tables, Logic Gates, SoP and PoS form, Basic Verilog

Week 2:
 K-Map, Minimization of SoPs, Incompletely Specified Functions, Number Representation, Unsigned Numbers

Week 3:
Multiplexers, Decoders, Encoders. Verilog modeling and simulation.

Week 4:
Sequential Design Elements, SR Latch, D Latch, D Flip Flop.

Week 5:
CMOS, Fundamentals of timing analysis, Setup and Hold time, Registers, Counters, Shift Registers, Design Examples, Synchronous Sequential Circuits,  Canonical Model of a State Machine, Types of State Machines, State Table,  Moore and Mealy Model

Week 6:
State Assignment, State Minimization, State Machine Examples, State Diagram, Design Principles, Timing a digital circuit,
Detailed Design Example, Detailed Timing Analysis,

Week 7:
Detailed design of a digital system. Datapath and control design. Top-down design methodology. Verilog modeling of state machines.

Week 8:
Optimization for Timing , Area vs Delay tradeoff, Pipelining, Parallelism, Pipelining vs Parallellism,

Week 9:
Number representation, Addition/Subtraction/Multiplication, Memory Digital System, Examples, Review

To access the content, please enroll in the course.

Faculty

Shankar Balachandran


Hello! I am currently an Associate Professor in the Computer Science and Engineering Department at IIT Madras. I received Ph.D. in Electrical Engineering from the University of Texas at Dallas in 2005 and B.E. in Computer Science and Engineering from the University of Madras in 1998. My research interests span computer architecture, VLSI design automation, high performance computing, linear algebra, parallel algorithms and combinatorial optimization.

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