Synthesis of Digital Systems

Start Date
22/01/2018

End Date
13/04/2018

Enrollment End Date
13/04/2018

No. of
Enrollments
344 students

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syllabus uploaded

Created by

Preeti Ranjan Panda
Indian Institute of Technology - Delhi
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Course Language
English
Course Type
Scheduled
Video transcripts
English
Course Category
Engineering
Learning Path
Undergraduate
Course Length
30 Hours
Weekly time commitments
20 Hours
Course Completion
Yes, after passing all tests.
Exam Date
To be announced
Credits
0

40

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Weekly Reading list

Overview

For certification please click here

Last date for enrollment: January 22, 2018

 
 
ABOUT THE COURSE:

 


This course is about the automatic generation of digital circuits from high-level descriptions. Modern electronic systems are specified in Hardware Description Languages and are converted automatically into digital circuits. We will introduce the VHDL Hardware Description Language, and follow it up with a discussion of the basics of synthesis topics including High-level Synthesis, FSM Synthesis, Retiming, and Logic Synthesis.

INTENDED AUDIENCE: None

CORE/ELECTIVE: Elective

UG/PG: PG Course. Also open to senior UG students.

PREREQUISITES: Pre-requisite courses: 1. Digital Design (or Logic Design) 2. Data Structuresl

INDUSTRY SUPPORT: Synopsys, Cadence Design Systems, Mentor Graphics, Intel, NXP, IBM

To access the content, please enroll in the course.

Faculty

Preeti Ranjan Panda


Preeti Ranjan Panda received his B. Tech. degree in Computer Science and Engineering from the Indian Institute of Technology Madras and his M. S. and Ph.D. degrees in Information and Computer Science from the University of California at Irvine. He is currently a Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. He has previously worked at Texas Instruments, Bangalore, India, and the Advanced Technology Group at Synopsys Inc., Mountain View, USA, and has been a visiting scholar at Stanford University. His research interests are: Embedded Systems Design, CAD/VLSI, Post-silicon Debug/Validation, System Specification and Synthesis, Memory Architectures and Optimisations, Hardware/Software Codesign, and Low Power Design. He is the author of two books: Memory issues in Embedded Systems-on-chip: Optimizations and Exploration (Kluwer Academic Publishers) and Power-efficient System Design (Springer). He is a recipient of an IBM Faculty Award and a Department of Science and Technology Young Scientist Award. Research works authored by Prof. Panda and his students have received several honours, including Best Paper nominations at CODES+ISSS, DATE, ASPDAC, and VLSI Design Conference, and Most downloaded paper of ACM TODAES journal. Prof. Panda has served on the editorial boards of IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) , ACM Transactions on Design Automation of Electronic Systems (TODAES) , IEEE Embedded Systems Letters and International Journal of Parallel Programming (IJPP), and as Technical Program co- Chair of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) and International Conference on VLSI Design and Embedded Systems (VLSI Design). He has also served on the technical program committees and chaired sessions at several conferences in the areas of Embedded Systems and Design Automation, including DAC, ICCAD, DATE, CODES+ISSS, IPDPS, ASPDAC, and EMSOFT.

COURSE LAYOUT:

Week 1  :  Course Outline and Introduction to VLSI Design Automation
Week 2  :   Hardware Description Languages and VHDL
Week 3  : Specifying Behaviour and Structure in HDL
Week 4  :  Introduction to High-level Synthesis
Week 5  :  Compiler Transformations in High-level Synthesis
Week 6  :  Scheduling
Week 7  :  Register Allocation and Timing Issues
Week 8  :  Finite State Machine Synthesis
Week 9  :  The Retiming Problem
Week 10  :  Introduction to Logic Synthesis and Binary Decision Diagrams
Week 11  :  Two-level and Multi-level Logic Optimisation
Week 12  :  Technology Mapping, Timing Analysis, and Physical Synthesis

SUGGESTED READING MATERIALS:

•    Giovanni de Micheli, Synthesis and
•    Optimization of Digital Circuits, McGraw Hill
 

 

CERTIFICATION EXAM :
  • The exam is optional for a fee.
  • Date and Time of Exams: April 28 (Saturday) and April 29 (Sunday) : Morning session 9am to 12 noon; Afternoon session: 2pm to 5pm
  • Exam for this course will be available in one session on both 28 and 29 April.The exact session it will be available in (FN/AN) - we shall inform by first week of January 2018.
  • Registration url: Announcements will be made when the registration form is open for registrations.
  • The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published.

CERTIFICATION:

  • Final score will be calculated as : 25% assignment score + 75% final exam score
  • 25% assignment score is calculated as 25% of average of  Best 8 out of 12 assignments
  • E-Certificate will be given to those who register and write the exam and score greater than or equal to 40% final score. Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IITD.It will be e-verifiable at nptel.ac.in/noc.

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