Week 1: Instruction execution fundamentals, Von-Neumann architecture, concept of memory and addressing. Performance measurement of computer hardware-MIPS, IPC, CPI, benchmarks. Speed-up Law. Instruction set principles, classification of instructions, addressing modes, instruction set encoding, MIPS instruction set, RISC vs CISC architectures.
Week 2: Concept of instruction pipelining, RISC instruction set, RISC 5 stage pipeline, pipeline hazards, operand forwarding, branch prediction techniques, basic MIPS pipeline
Week 3: MIPS pipeline for handling multi-cycle operations, Design issues with multi-cycle pipeline. Case Study: MIPS R4000 pipeline. Introduction to gem5 simulator
Week 4: Compiler techniques to exploit ILP, pipeline scheduling, loop unrolling, advanced branch prediction schemes, dynamic scheduling, Tomasulo’s approach, hardware base speculation, VLIW approach for multi-issue
Week 5: Multithreading-fined grained and coarse grained, superscalar and super pipelining, hyperthreading. Vector architectures, organizations and performance tuning. GPU architecture and internal organization, Elementary concepts in CUDA programming
Week 6: Introduction to memory hierarchy, locality of reference, cache memory fundamentals, cache performance parameters. Block level issues -mapping, identification, cache replacement techniques, write strategy, types of misses-compulsory, capacity, conflict misses.
Week 7: Basic cache optimizations by adjusting cache size, block size, associativity. Advanced cache optimizations-way prediction, pipelined and non-blocking caches, multi-banked caches, critical word first, early restart approaches, hardware pre-fetching, write buffer merging.
Week 8: Introduction to TCMP, NoC, topology, routing, flow control, virtual channels, input buffered router micro-architecture. Input and output selection strategies, allocators and arbiter algorithms for crossbar switch.