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Swayam Central

Digital IC Design

By Prof. Janakiraman   |   IIT Madras
This is a most fundamental Digital Circuit Design course for pursing a major in VLSI. We do not deal with any Verilog coding during this course and instead discuss transistor level circuit design concepts in great detail. Over learning objectives of this course are: 
  • Characterize the key delay quantities of a standard cell 
  • Evaluate power dissipated in a circuit (dynamic and leakage)
  • Design a circuit to perform a certain functionality with specified speed
  • Identify the critical path of a combinational circuit
  • Convert the combinational block to pipelined circuit
  • Calculate the maximum (worst case) operating frequency of the designed circuit
INTENDED AUDIENCE : Any student interested in Circuit Design as applied to VLSI Design
PREREQUISITES : A course on digital logic design is a must for doing this course.
INDUSTRY SUPPORT : All VLSI Design companies

Learners enrolled: 813

SUMMARY

Course Status : Upcoming
Course Type : Elective
Duration : 12 weeks
Start Date : 27 Jan 2020
End Date : 17 Apr 2020
Exam Date : 26 Apr 2020
Enrollment Ends : 03 Feb 2020
Category :
  • Electrical, Electronics and Communications Engineering
  • Level : Undergraduate
    This is an AICTE approved FDP course

    COURSE LAYOUT

    Week 1: The CMOS Inverter construction and Voltage Transfer Characteristics Week 2: Resistance and Capacitance and transient response. Week 3: Dynamic, Short Circuit and Leakage power – Stacking Effect Week 4: Combinational Circuit Design and capacitance Week 5: Parasitic Delay, Logical Effort and Electrical Effort Week 6: Gate sizing and Buffering Week 7: Asymmetric gate, Skewed gates, Ratio’ed logic Week 8: Dynamic Gates and Domino logic and Static Timing Analysis Week 9: Sequential circuits and feedback. Various D flip flop circuits – Static and Dynamic Week 10:Setup and Hold Time measurement. Timing analysis of latch/ flop based systems Week 11:Adders – Mirror adder, Carry Skip adder, Carry Select adder, Square Root adder Week 12:Multipliers – Signed and Unsigned arithmetic, Carry Save Multiplier implementation

    BOOKS AND REFERENCES

    NILL

    INSTRUCTOR BIO

    Prof. Janakiraman

    IIT Madras
    Prof. Janakiraman Viraraghavan is an Assistant Professor at the Department of Electrical Engineering, IIT Madras and is part of the Integrated Circuits and Systems (iCS) group. His research interests include porting machine-learning algorithms on to hardware and statistical analysis in VLSI. He also has a keen interest in Microprocessors and Programming in general.

    COURSE CERTIFICATE

    • The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.
    • The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).
    Date and Time of Exams: 26th April 2020, Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.
    • Registration url: Announcements will be made when the registration form is open for registrations.
    • The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.
    • Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

    CRITERIA TO GET A CERTIFICATE:
    • Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course.
    • Exam score = 75% of the proctored certification exam score out of 100
    • Final score = Average assignment score + Exam score

    YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75.
    • If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.
    • Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Madras. It will be e-verifiable at nptel.ac.in/noc
    • Only the e-certificate will be made available. Hard copies will not be dispatched.

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